1. Field of the Invention
The present invention relates to a voltage switching circuit and more specifically to a voltage switching circuit for use in non-volatile semiconductor devices that utilize a voltage higher than supply voltages for NAND cells, NOR cells, DINOR cells, or AND cells.
2. Description of the Related Art
Devices that use a boosted voltage higher than a supply voltage, typically non-volatile semiconductor devices, need a circuit that allows one interconnect line to charge selectively to ground voltage, a supply voltage Vcc, or a high voltage more than the supply voltage. An example of a conventional voltage switching circuit having such a function is illustrated in FIG. 1.
The voltage switching circuit of FIG. 1 comprises a first circuit consisting of a P-channel transistor QP1 and an N-channel transistor QN1 which are enhancement-mode devices and connected together at a node N1, a second circuit, or a high voltage output circuit, connected to an output node N2, and a third circuit consisting of an N-channel transistor QD3 which is a depletion-mode device having a thick gate insulating film and connected between the nodes N1 and N2. The thick gate insulating film of the transistor QD3 is intended to withstand a high voltage output from the high-voltage output circuit 20 to the drain side of QD3.
In the first circuit, the transistor QP1 has its source and substrate connected together to the supply voltage Vcc, its gate connected to receive a signal Sig1, and its drain connected to the node N1, while the transistor QN1 has its source connected to ground (0 V), its gate connected to receive a signal Sig2, and its drain connected to the node N1.
In the second circuit, or the high voltage output circuit 20, a signal Sig3 is input and a high voltage VPP is output to the node N2. The high voltage VPP is used as a program voltage for a non-volatile semiconductor device.
In the third circuit, the transistor QD3 has its source connected to the node N1, its gate connected to receive a signal Sig6, and its drain connected to the node N2. The third circuit consisting of QD3 is closely related to the main part of the voltage switching circuit of the present invention as will be shown later and is therefore particularly indicated enclosed by broken line 10.
The operation of the voltage switching circuit shown in FIG. 1 will be described next. The signals Sig1, Sig2, Sig3 and Sig6 are set to go from Vcc (high level) to 0 volts (low level) or vice versa. In some cases, the signal Sig6 can take a voltage # higher than 0 volts as its high level.
In the first circuit, when both the signals Sig1 and Sig2 go high, QP1 turns off and QN1 turns on, causing the node N1 to go to 0 volts. On the other hand, when the signals Sig1 and Sig2 go low, QP1 turns on and QN1 turns off, so that the node N1 goes to Vcc. When the signal Sig1 goes high and the signal Sig2 goes low, both QP1 and QN1 turn off, so that the node N1 is placed in the floating (high impedance) state. In this manner, 0 volts, Vcc or high-impedance state can be output to the node N1 through the use of the signals Sig1 and Sig2.
In the second circuit, when the input signal Sig3 to the high-voltage output circuit 20 is raised to the high level, a high voltage VPP is output to the node N2. On the other hand, when the signal Sig3 goes low, the node N2 is placed in the high-impedance state.
In the third circuit, when the signal Sig6 goes high, the transistor QD3 turns on, so that the path between the nodes N1 and N2 is rendered conductive. When the signal Sig6 goes low, the transistor QD3 goes into the nonconductive state, causing the path between the nodes N1 and N2 to be cutoff.
Although the operation of each of the first, second and third circuits has been described separately, the correspondence between the levels of the signals Sig1, Sig2, Sig3 and Sig6 and the output voltages of the conventional voltage switching circuit can be represented as follows:    (a) [Vcc, 0V, 0V, #]  [no output voltage (high-impedance state)]    (b) [Vcc, Vcc, 0V, #]  [output voltage=0V]    (c) [0V, 0V, 0V, Vcc]  [output voltage=Vcc]    (d) [0V, 0V, Vcc, 0V]  [output voltage=VPP]
The voltages within [ ] correspond to Sig1, Sig2, Sig3, and Sig6, respectively. In the case of (a) and (b), the voltage level # of Sig6 has only to be higher than 0 volts.
The feature of the voltage switching circuit shown in FIG. 1 is the provision of the depletion transistor QD3 between the output node N2 to which the high voltage VPP is output and the node N1 to which voltages of Vcc or less are applied. The implementation of cutoff of the path between the nodes N1 and N2 through a single transistor allows the circuit pattern area to be reduced.
In FIGS. 2A and 2B there is illustrated the operation of the third circuit 10. As described previously, in order for the voltage switching circuit to output desired voltages, the transistor QD3 is required to display such characteristics as indicated by dotted arrows in FIGS. 2A and 2B.
Assume here that the gate voltage of QD3 is Vg, the source voltage is Vs, and the drain voltage is Vd. Then, Vg corresponds to the voltage of Sig6, Vs to the voltage at the node N1, and Vd to the voltage at the node N2. As shown in FIG. 2A, therefore, the transistor QD3 should be rendered nonconductive when [Vg, Vs, Vd]=[0V, Vcc, VPP] and, as shown in FIG. 2B, the source supply voltage Vcc should be transferred to the drain when [Vg, Vs]=[Vcc, Vcc].
When the cutoff characteristic of QD3 shown in FIG. 2A is obtained, leakage current associated with high voltage VPP will flow from the drain to the source, resulting in the VPP level dropping. When the conductive characteristic of QD3 shown in FIG. 2B is not obtained, the output voltage Vcc of the voltage switching circuit is lowered.
In general, when Vcc is high, (Vg−Vs)=−Vcc in FIG. 2A increases in the negative direction and as a result the margin for the cutoff characteristic of QD3 increases, allowing the absolute value of the threshold voltage (a negative value) of the transistor QD3 to be increased. For this reason, the Vcc transfer state (on state) shown in FIG. 2B can be achieved with a sufficient margin. However, in order to achieve the cutoff characteristic of FIG. 2A with Vcc decreased, it is required to decrease the absolute value of the threshold voltage of QD3. Thus, the margin for the threshold voltage of QD3 for the Vcc transfer state decreases with decreasing Vcc.
That is, in FIG. 2A, Vg−Vs (0V−Vcc=−Vcc) required to turn off the depletion transistor QD3 approaches 0 volts with decreasing Vcc, which requires the threshold voltage of QD3 to be set close to 0 volts to cut off the third circuit 10. Therefore, the margin for the Vcc transfer state decreases.
In recent years, with decreasing power dissipation of semiconductor integrated circuits, the supply voltage used has been increasingly lowered, which involves difficulties in satisfying the characteristics of the n-channel depletion transistor QD3 shown in FIGS. 2A and 2B. For this reason, such circuits, as shown in FIGS. 3 and 4, have come into use which involve many components instead of using a depletion transistor.
The circuit of FIG. 3 is a voltage switching circuit which uses a third circuit 10a that is composed of an n-channel enhancement transistor QN2 in place of the n-channel depletion transistor QD3 and a high voltage generation circuit 25 which is responsive to the signal Sig6 to provide a high voltage to the gate of QN2. With the use of the enhancement transistor, the threshold voltage becomes positive, which allows the circumvention of the problem of reduced margin for threshold voltage resulting from lowered supply voltage.
The circuit of FIG. 4 is a voltage switching circuit which uses as a third circuit 10b an n-channel enhancement transistor QN3 having its gate connected to receive a signal Sig7 in place of the depletion transistor QD3 and a transfer gate consisting of a p-channel enhancement transistor QP2 having its gate connected to receive a signal Sig8 and its substrate connected to the output of an n-well voltage control circuit 30. In the circuit shown in FIG. 4 as well, an enhancement transistor is used; thus, the threshold voltage becomes positive, allowing the circumvention of the problem of reduced margin for threshold voltage resulting from lowered supply voltage.
However, the voltage switching circuit shown in FIG. 3 is accompanied by an increase in the pattern area because of the provision of the high voltage generation circuit 25. Likewise, the pattern area of the voltage switching circuit of FIG. 4 is increased by the n-well voltage control circuit 30. Both the voltage switching circuits suffer from a significant increase in the pattern area in comparison with the circuit of FIG. 1.
As described above, the conventional voltage switching circuits for use in non-volatile semi-conductor memory devices are not allowed to use a single depletion transistor under low supply voltages because of the reduced threshold voltage margin. On the other hand, the use of an enhancement transistor to increase the threshold voltage margin is accompanied by an increase in the pattern area and consequently in the chip area.
The object of the present invention is to provide a voltage switching circuit for use in non-volatile semiconductor devices which is large in operation margin without being accompanied by an increase in the chip area.